In recent years, various radio communication systems have appeared with the diffusion and high performance of information processing equipment. For those radio communication systems, there have been proposed software radio devices in which signal processing of transmission and reception necessary for the radio communication is realized by software, and the software is exchanged to another software to deal with plural different wireless systems.
Incidentally, in order to realize the recent radio communication system by software, the versatility and the high processing performance of the processor are required, and there arises such a problem that it is difficult to realize the radio communication system by software in the versatile processor presently used in a personal computer or a server. In addition, a circuit scale that can be realized by an LSI (large-scale integration) is presently expanded with a progress of the semiconductor manufacturing technique, and an LSI that effectively uses a large circuit has been demanded.
Japanese Patent Laid-Open No. H11 (1999)-22043 and Japanese Patent Laid-Open No. 2003-318802 disclose examples in which the above problem is solved by using the LSI that changes the configuration information which designates how the hardware should be structured to change the operation as represented by an FPGA (field-programmable gate array). In the above prior art, because it is possible to change the hardware according to the configuration information in the circuit represented by the FPGA to realize a structure similar to the dedicated circuit, it is expected that the required performance can be achieved.
In addition, as the LSI that improves the processing performance by effectively using a large circuit, attention has been paid to a technique that is called “reconfigurable LSI” among the LSIs that change the operation by changing the configuration information that designates how the hardware should be changed. The dynamic configuration control structure of the reconfigurable LSI is disclosed in Japanese Patent Laid-Open No. 2001-312481.
The above prior art discloses a control structure for autonomously conducting dynamic reconfiguration with no intervention of another controller or CPU in order to improve the throughput. In the control structure, there is a control method for a two-dimensional array having two kinds that consist of processing cells having the processing function, and switching cells that switch over a flow of data between the processing cells. In the structure, in order to conduct the dynamic reconfiguration, the structure of the transition table that is in the configuration state set by a user is in proportion to the number of state transitions.
In the conventional methods disclosed in Japanese Patent Laid-Open No. H11 (1999)-22043 and Japanese Patent Laid-Open No. 2003-318802, because the existing FPGA and PLD (programmable logic device) are assumed, there is required a relatively long period of time for switching over the configuration. For that reason, the switching of the configuration is not executed when one communication system is conducted, and the configuration is switched over only when the wireless system is switched over. Japanese Patent Laid-Open 2001-312481 discloses no wireless system. In this case, for example, circuits for transmission, reception, and synchronization and demodulation which are processing during reception do not operate at the same time, but it is necessary to prepare both of those circuits in advance. For that reason, there arises such a problem that a circuit area is increased. Also, the conventional method disclosed in Japanese Patent Laid-Open No. 2001-312481 suffers from problems on the versatility, the hardware capacity, and the user interface in the reconfigurable circuit system. Those problems will be described below.
A first problem resides in that the above method cannot be applied to the cells having a structure that switches over the flow of data within the processing cells. As the cell structure, although the function of switching over the flow of data within the processing cell is included in the structure, the function does not inhibit the reality, and therefore there is the difficulty in the versatility.
A second problem resides in the table structure that expresses the state transition of the configuration within a module that controls the dynamic reconfiguration. In the conventional method, because the table capacity is proportional to the number of state transitions and the control logic is also complicated, the LSI is recreated when the number of state transitions is increased. In general, in the state transition expression, because the number of state transitions is proportional to the second power of the state number, the flexibility to a change in the specification in the future and the versatility of the applied range are lost so far as the method applies that structure. This makes it difficult to change the configuration after the LSI has been manufactured to perform the variety of the system equipment.
A third problem resides in that a method of issuing a transition event (trigger) to the reconfiguration control module from the two-dimensional array is not particularly disclosed, and the usability of the user who prepares the configuration on the two-dimensional array is not considered.
A fourth problem resides in that a method of designating another operation together with the state transition, for example, a method of conducting the interrupt request operation to the CPU (central processing unit) is not disclosed, and the interlocking operation with the CPU is not considered.